EC architecture

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EC architecture


With the evolution of technology, PC system architecture has progressed from 8-bit to 64-bit, and the interface between the processor and system devices has changed from parallel to serial connections. The interface between the EC (Engineer Controller) and the system also changes with the system architecture. Therefore, this article explains the EC's interface and its functions to help beginners better understand the EC's role in the system.


  • System Architecture

There are two methods for connecting the EC and the system BIOS: Independence BIOS and Shared BIOS. The difference is that with Independence BIOS, the BIOS and EC firmware have their own independent flash memory, meaning the EC chip needs to contain flash memory; Shared BIOS means that the BIOS and EC firmware share the same BIOS flash memory.



  • PC XT/AT

The PC XT/AT system architecture was designed for a 16-bit CPU. It employed a parallel data transfer design, requiring 16 address/data lines for the 16-bit CPU. At the time, there were two schools of thought: serial and parallel transfer. Because the system speed was not fast, the latency in hardware transfer of 16 address/data lines wouldn't cause data errors, and serial transfer was too slow. Therefore, parallel transfer was adopted. The EC (External EC) was connected to the PC XT/AT's address/data lines, much like a PC peripheral [e.g., a printer].

 

 

  • PCI / LPC / ISA Flash

The PCI system architecture is used for 32-bit CPUs. The system still uses a parallel data transfer design. For slower 8/16-bit peripherals, LPC (Low Pin Count) is used instead of the PCI transfer protocol, but with some modifications: 32-bit is changed to 16-bit, and the 32 address/data lines are reduced to 4 address/data lines. Therefore, transferring one data item requires approximately 17 clock cycles.

Because the EC is an 8-bit PC peripheral, it uses an LPC connection to the PC. However, the connection interface between the EC and the FLASH memory remains unchanged. 

      


  • PCI Express / LPC / SPI Flash

In PC systems where CPU speeds and memory sizes have continuously increased, the parallel data transmission design of the PCI system architecture, regardless of whether the transmission speed is increased or the transmission frequency is increased from 32-bit to 64-bit, still struggles to avoid data errors due to hardware transmission delays. Therefore, the system switched to serial transmission PCI Express. Because PCI Express still uses the LPC interface for 8/16-bit peripherals, the interface between the PC and EC remains unchanged. However, to reduce system space requirements, the EC changed its FLASH transmission interface to SPI serial transmission.

 


  • PCI Express / eSPI / SPI Flash

In addition to faster CPUs and larger memory in PC systems, power saving is becoming increasingly important. The system has been upgraded from 3.3V LPC to 1.8V eSPI, and the speed has been increased to 66MHz.




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