EC Required Knowledge - LPC

EC Required Knowledge
The first step for a software engineer is to thoroughly understand the relevant specifications, just as understanding the requirements is essential before developing software. Similarly, an EC engineer needs to have a clear understanding of LPC, SMBUS, PS2, and Smart Battery before moving on to the next step.

LPC Specification

This chapter focuses on the LPC Interface, allowing readers to understand its operating principles and pin functions. Understanding the LPC Interface is essential to finding solutions when problems arise.

• LPC characteristics

• X-BUS interface compatible with legacy systems

• It can be addressed up to 4GB, and the BIOS is not limited to 1MB, nor is the memory device limited to 16MB.

• It can operate correctly without the need for special driver installation on the operating system.

• If I/O or MEMORY instructions take a long time, consider using LPC to enter a wait state.

• LPC-supported devices

• SUPER I/O – Floppy disk control interface, IR, KBC

• Audio – AC97

• Memory device – BIOS Flash

• System Manager Controller

• LPC block diagram

The system's instructions are transmitted from the CPU to the HOST-Bridge (Northbridge chip), then via the PCI Bus to the PCI-Bridge (Southbridge chip), which is also the HOST in the diagram above. The HOST then translates the PCI instructions into LPC instructions and transmits them to the LPC device, thus completing the instruction transfer.

• LPC hardware pinout

Signal	Direction		Description
	Peripheral	Host
LAD[3:0]	I/O	I/O	Multi-functional pin. Can be used for commands, addresses, and data.
LFRAME#	I	THE	Indicates the start and end of LPC instruction transmission.
LRESET#	I	I	PCI interface RESET signal
LCLK	I	I	Signal source for LPC interface [33MHz]
LDRQ#	THE	I	DMA is supported and control of the PCI Bus must be obtained before it can be used.
SERIRQ	I/O	I/O	For LPC devices, to issue an interrupt signal, if a device using IRQ12 needs to send an interrupt signal, pulling the LOW pin at CLOOK (the 12th clock cycle) is equivalent to IRQ12.
CLKRUN#	OF	I/O	When the system requests the device to stop working, it will pull the requesting device's CLKRUN to LOW.
SMEs#	OF	I/O	The system is required to wake up from sleep mode.
LPCPD#	I	I/O	Put the LPC device into power-saving mode
LSMI#	O/D	I	System interrupts are consistent with SERIRQs, transmitting interrupt signals according to the requirements of the LPC device.

• LPC Transmission Protocol

LPC的指令可分為Memory Read / Write、I/O Read / Write、DMA Read / Write、BUS Master Memory Read / Write及BUS Master I/O Read / Write等如Table 3。

All these diverse instructions are transmitted to the LPC device via a combination of four instruction lines. Therefore, each instruction takes several clock cycles to complete. The time from the start to the completion of an LPC instruction is called an instruction cycle. (See Figure 2)

An LPC instruction cycle includes START, CYCTYPE, ADDR, TAR, SYNC, DATA, and TAR.

Name	CLOCK	Description
START	1	Indicate the starting point
CYCLE TYPE	1	Indicates the direction and magnitude of transmission
ADDR	8	Address [Defineable up to 4G]
TAKE	2	Instruction of BUS control
SYNC	1-n	Synchronous inspection
DATA	2	material

• Description of the START field –

The PCI cycle indicator field usually needs to be used in conjunction with the cycle type to understand the function of the PCI cycle, except for firmware read/write, which can be directly determined from the Start field.

BIT[3:0]	Define
0000	Start of cycle for a start
0010	Agree bus master 0
0011	Agreed with bus master 1
1111	Stop / Abort

• CYCLE TYPE field description

BIT[3:2]	BIT[1]	Define
00	0	I/O Read
00	1	I/O Write
01	0	Memory Read
01	1	Memory Write
10	0	DMA Read
10	1	DMA Write

• SIZE field description

Bits[1:0]	Size
00	1 bytes
01	2 bytes
11	4 bytes

• SYNC's field description

BIT[3:0]	Define
0000	Ready
0101	Short Wait
0110	Long Wait
1001	Ready More (DMA Only)
1010	Error

• Introduction to each instruction period

instruction	ST	TP	AD / SZ	TAKE	SYNC	DATA	TAKE	SUM
MM Read	1	1	8	2	5	2	2	21
MM Write	1	1	8	2	2	1	2	17
IO Read	1	1	4	2	1	2	2	13
IO Write	1	1	4	2	2	1	2	13
DMA Read 8	1	1	2	2	2	1	2	11
DMA Read 16	1	1	2	4	4	2	4	18
DMA Read 32	1	1	2	8	8	4	8	32
DMA Write 8	1	1	2	2	2	1	2	11
DMA Write 16	1	1	2	2	2	4	2	14
DMA Write 32	1	1	2	2	4	8	2	20

• ST - Start Nibble.

• TP – Type Nibble.

• AD/SZ – Address Nibble or Size Nibble

• Firmware Memory Transfer Protocol

Firmware Memory only has memory read and write functions. The main difference between Firmware Memory and LPC memory read and write functions is that Firmware Memory's read and write functions have been expanded from 1, 2, 4, 8 to 16, 128 bits, and the IDSEL field can be used to select which device to read and write memory to.

Firmware Memory Cycle –

The Firmware Memory field –

• START field –

BIT[3:0]	Define
0000	Start of cycle for a start
0010	Agree bus master 0
0011	Agreed with bus master 1
1101	Start cycle for firmware memory read cycle
1110	Start cycle for firmware memory write cycle
1111	Stop / Abort

• IDSEL field – BIT[3:0] Select device

• MADDR field – Read position

• MSIZE field - Read number of bits

Bits[3:0]	Size
0000	1 bytes
0001	2 bytes
0010	4 bytes
0100	16 bytes
0111	128 bytes

Firmware Memory Read Cycle –

Firmware Memory Write Cycle –

Serial IRQ transmission protocol

Serial IRQ Working Mode

• Quiet (Active Mode) When an IRQ occurs, the device only needs to issue an IRQ (pull the signal low) to enter Tri-State. This is more power-efficient. However, some chipsets or EC microprocessors take longer to return to Active from Tri-State, which can cause IRQ misses.

• Continuous (Idle Mode) When an IRQ occurs, the device needs to send an IRQ (low-signal) and continuously sample a stop frame until the host device confirms receipt; otherwise, it needs to continuously send IRQs to the host device.