FPGA sample - Lattice I2C IP (EFB) #2

-

 Lattice Diamond Setting

  • Click "IPexpress button" and select "EFB" IPX
  • Select "Project Path" (source code files), "File Name" and "Module Output" is Verilog
  • Click "Customize"

  • Select Primary I2C
    • EFB have 2 I2C controller, suggestion use primary I2C
  • "EFB Enable" tab → "EFB Function Enable" Field → Click "Primary User"

  

  • Configuration Primary I2C
    • Speed is 400KHz
    • Slave Address is "0001001"
  • "I2C" tab → "Primary I2C " Field → "I2C Bus Preformance" is 400KHz → "Slave Address" is 7'b0001001
  • Click "Generate" to generate hardware I2C code
  • Founad hardware I2C IPX in your project files

 範例程式碼

  •  宣告 EFB-IP

  1.  /***********************************************************************
  2.  *                                                                      *
  3.  * EFB Module Instanitiation                                            *
  4.  *                                                                      *
  5.  ***********************************************************************/	   
  6. wire rst_p = ~RST_N ;
  7. efbi2c UUT  ( .wb_clk_i (CLK      ),
  8.               .wb_rst_i (rst_p    ),
  9.               .wb_cyc_i (wb_cyc_i ),
  10.               .wb_stb_i (wb_stb_i ),
  11.               .wb_we_i  (wb_we_i  ),
  12.               .wb_adr_i (wb_adr_i ),
  13.               .wb_dat_i (wb_dat_i ),
  14.               .wb_dat_o (wb_dat_o ), 
  15.               .wb_ack_o (wb_ack_o ),      
  16.               .i2c1_scl (SCL      ),
  17.               .i2c1_sda (SDA      ),
  18.               .i2c1_irqo(i2c1_irq_o) );
  19.  
  • EFB-IP 的 address / data / control pin 訊號順序
  1.  /////////////////////////////////////////////
  2. //                                          //
  3. //    State Machines Sequential Block       //
  4. //                                          //
  5. //////////////////////////////////////////////   
  6. always @ (posedge CLK or negedge RST_N)
  7. begin 
  8. 	if(!RST_N)
  9. 	begin 
  10. 		wb_dat_i 	<= 8'h00;
  11. 		wb_stb_i 	<= 1'b0 ;
  12. 		wb_adr_i 	<= 8'h00;
  13. 		wb_we_i  	<= 1'b0;   
  14. 	end   
  15. 	else 
  16. 	begin 
  17. 		wb_dat_i 	<=  n_wb_dat_i;
  18. 		wb_stb_i 	<=  n_wb_stb_i;
  19. 		wb_adr_i 	<=  n_wb_adr_i;
  20. 		wb_we_i  	<=  n_wb_we_i ;
  21. 	end 
  22. end 
  24. always @ (posedge CLK or negedge RST_N)
  25. begin 
  26. 	if(!RST_N) 
  27. 	begin 
  28. 		c_state  	<= 10'h000;
  29. 		efb_flag 	<= 1'b0 ;
  30. 		dat_count	<= 8'd0;
  31. 	end  
  32. 	else 
  33. 	begin  
  34. 		c_state  	<= n_state   ;
  35. 		efb_flag 	<= n_efb_flag;
  36. 		dat_count 	<= n_dat_count ;
  37. 	end  
  38. end
  • EFB-IP state machine 加入 oem 程序碼
  1. //////////////////////////////////////////////
  2. //                                          //
  3. //    State Machines Combinational Block    //
  4. //                                          //
  5. //////////////////////////////////////////////   
  6. always @ ( * )
  7. begin 
  8. 		n_efb_flag    	= 1'b0 ; 
  9. 		n_state       	= c_state ; 
  10. 		n_dat_count   	= dat_count ;
  11. 		n_wb_dat_i    	= 8'h00;
  12. 		n_wb_stb_i    	= 1'b0 ;
  13. 		n_wb_adr_i    	= 8'h00;
  14. 		n_wb_we_i     	= 1'b0;
  15. 		n_temp0       	= temp0;
  16. 		i2c_cmd_d     	= i2c_cmd_q;
  17. 		i2c_check_d   	= i2c_check_q;
  18. 		i2c_data_d    	= i2c_data_q;  
  19. 		cmdVRMEn_d	  	= cmdVRMEn_q;	
  20.   
  21.     case(c_state)
  22.     `state0 : // I2C in idle 
  23.     begin 
  24. 		n_wb_dat_i 		= 8'h00;
  25.         n_wb_stb_i 		= 1'b0;
  26.         n_wb_adr_i 		= 8'h00;
  27.         n_wb_we_i  		= 1'b0;           
  28.         n_wb_stb_i 		= 1'b0;    
  29.         n_state 		= `state1 ;              
  30.     end   
  31.     
  32. 	`state1 : // Enable I2C Interface 
  33. 	begin 
  34. 		if (wb_ack_o && efb_flag) 
  35. 		begin
  36. 			n_wb_dat_i 	= `ALL_ZERO ;
  37. 			n_wb_adr_i 	= `ALL_ZERO ;
  38. 			n_wb_we_i 	= `LOW ;
  39. 			n_wb_stb_i 	= `LOW ;
  40. 			n_efb_flag 	= `LOW ;
  41. 			n_state 	= `state2;
  42. 		end
  43. 		else if(!wb_ack_o)
  44. 		begin
  45. 			n_efb_flag 	= `HIGH ;
  46. 			n_wb_adr_i 	= `MICO_EFB_I2C_CR;
  47. 			n_wb_dat_i 	= 8'h88;
  48. 			n_wb_we_i 	= `WRITE;
  49. 			n_wb_stb_i 	= `HIGH ; 
  50. 			n_state 	= c_state; 
  51. 		end
  52. 	end
  54. 	`state2 : // Clock Disable 
  55. 	begin 		
  56. 		if (wb_ack_o && efb_flag) 
  57. 		begin
  58. 			n_wb_dat_i 	= `ALL_ZERO ;
  59. 			n_wb_adr_i 	= `ALL_ZERO ;
  60. 			n_wb_we_i 	= `LOW ;
  61. 			n_wb_stb_i 	= `LOW ;
  62. 			n_efb_flag 	= `LOW ;
  63. 			n_state 	= `state3;
  64. 		end
  65. 		else if(!wb_ack_o)
  66. 		begin
  67. 			n_efb_flag 	= `HIGH ;
  68. 			n_wb_adr_i 	= `MICO_EFB_I2C_CMDR;
  69. 			n_wb_dat_i 	= 8'h04;
  70. 			n_wb_we_i 	= `WRITE;
  71. 			n_wb_stb_i 	= `HIGH ; 
  72. 			n_state 	= c_state; 
  73. 		end
  74. 	end
  75.   
  76. 	`state3 : // Wait for not BUSY  
  77. 	begin 
  78. 		if (wb_ack_o && efb_flag) 
  79. 		begin
  80. 			n_wb_dat_i 	= `ALL_ZERO ;
  81. 			n_wb_adr_i 	= `ALL_ZERO ;
  82. 			n_wb_we_i 	= `LOW ;
  83. 			n_wb_stb_i 	= `LOW ;
  84. 			n_efb_flag 	= `LOW ;
  85. 			if(wb_dat_o & ( `MICO_EFB_I2C_SR_BUSY) )
  86. 				n_state = c_state;
  87. 			else
  88. 				n_state = `state4;
  89. 		end
  90. 		else if(!wb_ack_o) 
  91. 		begin
  92. 			n_efb_flag 	= `HIGH ;
  93. 			n_wb_we_i 	= `READ_STATUS;
  94. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  95. 			n_wb_dat_i 	= 0 ;
  96. 			n_wb_stb_i 	= `HIGH ; 
  97. 			n_state 	= c_state; 
  98. 		end
  99. 	end
  100.   
  101. 	`state4 : // Discard data 1 
  102. 	begin 
  103. 		if (wb_ack_o && efb_flag) 
  104. 		begin
  105. 			n_wb_dat_i 	= `ALL_ZERO ;
  106. 			n_wb_adr_i 	= `ALL_ZERO ;
  107. 			n_wb_we_i 	= `LOW ;
  108. 			n_wb_stb_i 	= `LOW ;
  109. 			n_efb_flag 	= `LOW ;
  110. 			n_temp0 	= wb_dat_o; 
  111. 			n_state 	= `state5;
  112. 		end
  113. 		else if(!wb_ack_o) 
  114. 		begin
  115. 			n_efb_flag 	= `HIGH ;
  116. 			n_wb_we_i 	= `READ_DATA;
  117. 			n_wb_adr_i 	= `MICO_EFB_I2C_RXDR;
  118. 			n_wb_dat_i 	= 0 ;
  119. 			n_wb_stb_i 	= `HIGH ; 
  120. 			n_state 	= c_state; 
  121. 		end
  122. 	end
  123.  
  124.  
  125. 	`state5 : // Discard data 2 
  126. 	begin 
  127. 		if (wb_ack_o && efb_flag) 
  128. 		begin
  129. 			n_wb_dat_i = `ALL_ZERO ;
  130. 			n_wb_adr_i = `ALL_ZERO ;
  131. 			n_wb_we_i =  `LOW ;
  132. 			n_wb_stb_i = `LOW ;
  133. 			n_efb_flag = `LOW ;
  134. 			n_temp0 = wb_dat_o; 
  135. 			n_state = `state7;   // keep clock stretching disabled per PCN#10A-13
  136. 		end
  137. 		else if(!wb_ack_o) 
  138. 		begin
  139. 			n_efb_flag = `HIGH ;
  140. 			n_wb_we_i =  `READ_DATA;
  141. 			n_wb_adr_i = `MICO_EFB_I2C_RXDR;
  142. 			n_wb_dat_i =  0 ;
  143. 			n_wb_stb_i = `HIGH ; 
  144. 			n_state = c_state; 
  145. 		end
  146. 	end
  147.  
  148. 	`state7: // wait for data to come
  149. 	begin 	
  150. 		if (wb_ack_o && efb_flag) 
  151. 		begin
  152. 			n_wb_dat_i = `ALL_ZERO ;
  153. 			n_wb_adr_i = `ALL_ZERO ;
  154. 			n_wb_we_i =  `LOW ;
  155. 			n_wb_stb_i = `LOW ;
  156. 			n_efb_flag = `LOW ;
  157. 			if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)) 
  158. 				n_state = `state8;		   
  159. 			else
  160. 				n_state = c_state;
  161. 		end
  162. 		else if(!wb_ack_o)
  163. 		begin
  164. 			n_efb_flag = `HIGH ;
  165. 			n_wb_we_i =  `READ_STATUS;
  166. 			n_wb_adr_i = `MICO_EFB_I2C_SR;
  167. 			n_wb_dat_i =  0 ;
  168. 			n_wb_stb_i = `HIGH ; 
  169. 			n_state = c_state; 
  170. 		end
  171. 	end
  173. 	`state8: // Store i2C Command Information 
  174. 	begin 
  175. 		if (wb_ack_o && efb_flag) begin
  176. 			n_wb_dat_i 	= `ALL_ZERO ;
  177. 			n_wb_adr_i 	= `ALL_ZERO ;
  178. 			n_wb_we_i 	=  `LOW ;
  179. 			n_wb_stb_i 	= `LOW ;
  180. 			n_efb_flag 	= `LOW ;
  181. 			i2c_cmd_d 	= wb_dat_o; 
  182. 			n_state 	= `state9;
  183.        end
  184.        else if(!wb_ack_o)
  185. 	   begin
  186. 			n_efb_flag = `HIGH ;
  187. 			n_wb_we_i =  `READ_DATA;
  188. 			n_wb_adr_i = `MICO_EFB_I2C_RXDR;
  189. 			n_wb_dat_i =  0 ;
  190. 			n_wb_stb_i = `HIGH ; 
  191. 			n_state = c_state; 
  192. 		end
  193. 	end
  194.   
  195. 	`state9 : // Send ACK or NACK Based upon Command Receive & Wait for Stop `state 17 
  196. 	begin 
  197. 		if (wb_ack_o && efb_flag) 
  198. 		begin
  199. 			n_wb_dat_i 	= `ALL_ZERO ;
  200. 			n_wb_adr_i 	= `ALL_ZERO ;
  201. 			n_wb_we_i 	= `LOW ;
  202. 			n_wb_stb_i 	= `LOW ;
  203. 			n_efb_flag 	= `LOW ;
  204. 			
  205. 			// oem command
  206. 		end      
  207. 		else 
  208. 		begin if(!wb_ack_o)
  209. 			n_efb_flag 	= `HIGH ;
  210. 			n_wb_adr_i 	= `MICO_EFB_I2C_CMDR;
  211. 			n_wb_dat_i 	= {4'h0,~cmd_data,3'b100};    
  212. 			n_wb_we_i 	= `WRITE;
  213. 			n_wb_stb_i 	= `HIGH ; 
  214. 			n_state 	= c_state; 
  215. 		end
  216. 	end
  217.  
  218.  
  219. 	`state10 : // Command Valid 
  220. 	begin         
  221. 		if (wb_ack_o && efb_flag) 
  222. 		begin
  223. 			n_wb_dat_i 	= `ALL_ZERO ;
  224. 			n_wb_adr_i 	= `ALL_ZERO ;
  225. 			n_wb_we_i 	= `LOW ;
  226. 			n_wb_stb_i 	= `LOW ;
  227. 			n_efb_flag 	= `LOW ;
  228. 			if(wb_dat_o & ( `MICO_EFB_I2C_SR_TRRDY) )
  229. 				n_state = `state11;
  230. 			else if (~wb_dat_o[6])		// if stop bit
  231. 				n_state = `state2;
  232. 			else
  233. 				n_state = c_state;
  234. 		end
  235. 		else if(!wb_ack_o)
  236. 		begin
  237. 			n_efb_flag 	= `HIGH ;
  238. 			n_wb_we_i 	= `READ_STATUS;
  239. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  240. 			n_wb_dat_i 	= 0 ;
  241. 			n_wb_stb_i 	= `HIGH ; 
  242. 			n_state 	= c_state; 
  243. 		end
  244. 	end
  245.  
  246.  
  247. 	`state11: // Store checksum byte Information
  248. 	begin 	
  249. 		if (wb_ack_o && efb_flag) 
  250. 		begin
  251. 			n_wb_dat_i 	= `ALL_ZERO ;
  252. 			n_wb_adr_i 	= `ALL_ZERO ;
  253. 			n_wb_we_i 	= `LOW ;
  254. 			n_wb_stb_i 	= `LOW ;
  255. 			n_efb_flag 	= `LOW ;
  256. 			i2c_check_d = wb_dat_o;
  257. 			if(command_data == ~i2c_check_d) 
  258. 			begin			
  259. 				// oem command
  260. 			end 
  261. 			else
  262. 				n_state = `state17;
  263. 		end
  264. 		else if(!wb_ack_o)
  265. 		begin
  266. 			n_efb_flag 	= `HIGH ;
  267. 			n_wb_we_i 	= `READ_DATA;
  268. 			n_wb_adr_i 	= `MICO_EFB_I2C_RXDR;
  269. 			n_wb_dat_i 	= 0 ;
  270. 			n_wb_stb_i 	= `HIGH ; 
  271. 			n_state 	= c_state; 
  272. 		end
  273. 	end
  274.  
  275.  
  276. 	`state12: // Wait for TRRDY Bit 
  277. 	begin 
  278. 		if (wb_ack_o && efb_flag) 
  279. 		begin
  280. 			n_wb_dat_i 	= `ALL_ZERO ;
  281. 			n_wb_adr_i 	= `ALL_ZERO ;
  282. 			n_wb_we_i 	= `LOW ;
  283. 			n_wb_stb_i 	= `LOW ;
  284. 			n_efb_flag 	= `LOW ;
  285. 			if(wb_dat_o & ( `MICO_EFB_I2C_SR_TRRDY))
  286. 			begin
  287. 				// Read command
  288. 			end 
  289. 			else if (~wb_dat_o[6])
  290. 				n_state = `state2;		
  291. 			else
  292. 				n_state = c_state;
  293. 		end    
  294. 		else if(!wb_ack_o)
  295. 		begin
  296. 			n_efb_flag 	= `HIGH ;
  297. 			n_wb_we_i 	= `READ_STATUS;
  298. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  299. 			n_wb_dat_i 	= 0 ;
  300. 			n_wb_stb_i 	= `HIGH ; 
  301. 			n_state 	= c_state; 
  302. 		end
  303.     end
  304.  
  305. 	`state13: // Check for read or write operation Go to State15
  306. 	begin 	
  307. 		if (wb_ack_o && efb_flag) 
  308. 		begin
  309. 			n_wb_dat_i 	= `ALL_ZERO ;
  310. 			n_wb_adr_i 	= `ALL_ZERO ;
  311. 			n_wb_we_i 	= `LOW ;
  312. 			n_wb_stb_i 	= `LOW ;
  313. 			n_efb_flag 	= `LOW ;
  314. 			if(wb_dat_o & ( `MICO_EFB_I2C_SR_SRW))
  315. 				n_state = `state15;
  316. 			else
  317. 				n_state = c_state;
  318. 		end
  319. 		else if(!wb_ack_o)
  320. 		begin
  321. 			n_efb_flag 	= `HIGH ;
  322. 			n_wb_we_i 	= `READ_STATUS;
  323. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  324. 			n_wb_dat_i 	= 0 ;
  325. 			n_wb_stb_i 	= `HIGH ; 
  326. 			n_state 	= c_state; 
  327. 		end
  328. 	end
  329.  
  330.  
  331. 	`state14: 
  332. 	begin // Read Data
  333. 		if (wb_ack_o && efb_flag) 
  334. 		begin
  335. 			n_wb_dat_i 	= `ALL_ZERO ;
  336. 			n_wb_adr_i 	= `ALL_ZERO ;
  337. 			n_wb_we_i 	= `LOW ;
  338. 			n_wb_stb_i 	= `LOW ;
  339. 			n_efb_flag 	= `LOW ;
  340. 			n_dat_count = dat_count - 1;
  341. 			i2c_wr_data[n_dat_count] <= wb_dat_o;		  
  342. 			n_state 	= `state19;			 
  343. 		end
  344. 		else if(!wb_ack_o)
  345. 		begin
  346. 			n_efb_flag 	= `HIGH ;
  347. 			n_wb_we_i 	= `READ_DATA;
  348. 			n_wb_adr_i 	= `MICO_EFB_I2C_RXDR;
  349. 			n_wb_dat_i 	= 0 ;
  350. 			n_wb_stb_i 	= `HIGH ; 
  351. 			n_state 	= c_state; 
  352. 		end
  353.      end
  354. 	 
  355. 	`state15: // Send Data to Master
  356. 	begin 
  357. 		if (wb_ack_o && efb_flag) 
  358. 		begin
  359. 			n_wb_dat_i 	= `ALL_ZERO ;
  360. 			n_wb_adr_i 	= `ALL_ZERO ;
  361. 			n_wb_we_i 	= `LOW ;
  362. 			n_wb_stb_i 	= `LOW ;
  363. 			n_efb_flag 	= `LOW ;
  364. 			n_state 	= `state18;
  365. 		    n_dat_count = dat_count - 1 ;
  366. 		end
  367. 		else if(!wb_ack_o)
  368. 		begin
  369. 			n_efb_flag 	= `HIGH ;
  370. 			n_wb_adr_i 	= `MICO_EFB_I2C_TXDR;
  371. 			if(n_dat_count != 1)
  372. 				n_wb_dat_i = i2c_cmd_q;
  373. 			else
  374. 				n_wb_dat_i = i2c_data_q;
  375. 			n_wb_we_i 	= `WRITE;
  376. 			n_wb_stb_i 	= `HIGH ; 
  377. 			n_state 	= c_state; 
  378. 		end
  379.   end
  380.  
  381.  
  382.  
  383. 	`state16: // Send NACK Based upon Command Receive
  384. 	begin 	
  385. 		if (wb_ack_o && efb_flag) 
  386. 		begin
  387. 			n_wb_dat_i 	= `ALL_ZERO ;
  388. 			n_wb_adr_i	= `ALL_ZERO ;
  389. 			n_wb_we_i 	= `LOW ;
  390. 			n_wb_stb_i 	= `LOW ;
  391. 			n_efb_flag 	= `LOW ;
  392.         //  n_count_en 	= `LOW ;
  393. 			n_state 	= `state17;
  394. 		end
  395. 		else if(!wb_ack_o)
  396. 		begin
  397. 			n_efb_flag 	= `HIGH ;
  398. 			n_wb_adr_i 	= `MICO_EFB_I2C_CMDR;
  399. 			n_wb_dat_i 	= 8'h0C; 
  400. 			n_wb_we_i 	= `WRITE;
  401. 			n_wb_stb_i 	= `HIGH ; 
  402. 			n_state 	= c_state; 
  403. 		end
  404.      end
  405.  
  406.  
  407. 	`state17: // Wait till Stop is Send 
  408. 	begin 
  409. 		if (wb_ack_o && efb_flag) 
  410. 		begin
  411. 			n_wb_dat_i 	= `ALL_ZERO ;
  412. 			n_wb_adr_i 	= `ALL_ZERO ;
  413. 			n_wb_we_i 	= `LOW ;
  414. 			n_wb_stb_i 	= `LOW ;
  415. 			n_efb_flag 	= `LOW ;
  416. 			if(~wb_dat_o[6])
  417. 				n_state = `state2;
  418. 			else
  419. 				n_state = c_state;
  420. 		end
  421. 		else if(!wb_ack_o)
  422. 		begin
  423. 			n_efb_flag 	= `HIGH ;
  424. 			n_wb_we_i 	= `READ_STATUS;
  425. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  426. 			n_wb_dat_i 	= 0 ;
  427. 			n_wb_stb_i 	= `HIGH ; 
  428. 			n_state 	= c_state; 
  429. 		end
  430. 	end
  431.  
  432. 	`state18: // Wait for TxRDY flag and send data again if required 
  433. 	begin 	
  434. 		if (wb_ack_o && efb_flag) 
  435. 		begin
  436. 			n_wb_dat_i 	= `ALL_ZERO ;
  437. 			n_wb_adr_i 	= `ALL_ZERO ;
  438. 			n_wb_we_i 	= `LOW ;
  439. 			n_wb_stb_i 	= `LOW ;
  440. 			n_efb_flag 	= `LOW ;
  441. 			if ( dat_count == 8'h00) 	   
  442. 				n_state = `state16;	// Send Nack for Any More Read Request 
  443. 			else if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY ))
  444.      		    n_state = `state15;                   // Send Data  
  445. 			else
  446. 				n_state = c_state;
  447. 		end
  448. 		else if(!wb_ack_o)
  449. 		begin
  450. 			n_efb_flag 	= `HIGH ;
  451. 			n_wb_we_i 	= `READ_STATUS;
  452. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  453. 			n_wb_dat_i 	= 0 ;
  454. 			n_wb_stb_i 	= `HIGH ; 
  455. 			n_state 	= c_state; 
  456. 		end
  457.      end
  459.  
  460.    `state19: // Wait for TRRDY bit 
  461. 	begin  
  462. 		if (wb_ack_o && efb_flag) 
  463. 		begin
  464. 			n_wb_dat_i 	= `ALL_ZERO ;
  465. 			n_wb_adr_i 	= `ALL_ZERO ;
  466. 			n_wb_we_i 	= `LOW ;
  467. 			n_wb_stb_i 	= `LOW ;
  468. 			n_efb_flag 	= `LOW ;
  469. 	        if ( dat_count == 8'h00)
  470. 				n_state = `state16;		   
  471. 			else if(wb_dat_o & ( `MICO_EFB_I2C_SR_TRRDY) )
  472. 				n_state = `state14;
  473. 			else if (~wb_dat_o[6])
  474. 				n_state = `state2;
  475. 			else
  476. 				n_state = c_state;
  477. 		end 
  478. 		else if(!wb_ack_o)
  479. 		begin
  480. 			n_efb_flag 	= `HIGH ;
  481. 			n_wb_we_i 	= `READ_STATUS;
  482. 			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
  483. 			n_wb_dat_i 	= 0 ;
  484. 			n_wb_stb_i 	= `HIGH ; 
  485. 			n_state 	= c_state; 
  486. 		end
  487. 	end
  488. 	endcase
  489. end

 

 參考資料



 






留言

張貼留言

這個網誌中的熱門文章

EC 所需知識 - SMBUS

-
圖片
EC 所需知識 軟體工程師的第一步，先把相關的規範(Specification)了解清楚，就像開發一套軟體之前要先了解需求，才能做出一套符合需求的體。相同的EC工程師就是需要把 LPC / SMBUS / PS2 / Smart Battery 的相關知識，清楚明瞭再進下一步。 SMBUS SMBus [System Management Bus] 是由Intel所制訂的，主要由兩條線組成，其一為CLOCK線，另一條為DATA線。其作用是讓系統監控者透過SMBus來蒐集系統上裝置的資訊如電池的容量、CPU的溫度等，讓系統監控者可以依照所得的資訊通知作業系統做電源管理的處理。在筆記型電腦系統中的ACPI-EC為SMBus的主控者 [Host] 來蒐集SMBus上的裝置資訊回報給作業系統，讓作業系統依使用者的設定做系統電源的管理。 SMBus相關的規格包含SMBus、Smart Selector、Smart Charger及Smart Battery都是ACPI-EC工程師需要瞭解的規格，以下的章節將會詳盡的介紹各個規格的資訊。 SMBUS Specification Hardware Define SMBUS 的硬體線路 –SMBUS由二條線所組成，所有的SMBUS的裝置都並聯在SMBUS上，因此，SMBUS上的所有裝置都需要使用Open collection 或者 Open drain才允許跨接在SMBUS上面，因此線路上必須加上提升電阻來確認SMBUS上的訊號可以正確無誤的傳遞。 如同上圖，有時侯  SMBUS  上會有不同 VDD 的裝置，所以一般在輸入接腳會加稽納二極體保護裝置。不過大部分的作法，會使用電壓緩衝IC來處理不同電壓的 I2C 裝置。  SMBUS電氣上的要求 名稱 說明 值域 單位 下限 上限 VIL 輸入低電位 0.8 V VIH 輸入高電位 2.1 VDD V VOL 輸出為低電位 0.4 V IPULLUP 提升電流值 100 350 uA VDD 工作電壓 2.7 5.5 V SMBUS的時脈要求 名稱 ...
閱讀完整內容

EC 所需知識 - KBC

-
EC 所需知識 軟體工程師的第一步，先把相關的規範(Specification)了解清楚，就像開發一套軟體之前要先了解需求，才能做出一套符合需求的體。相同的EC工程師就是需要把 LPC / SMBUS / PS2 / KBC 等相關知識，清楚明瞭再進下一步。 Keyboard Controller 最早的鍵盤控制器是Intel 8042，主要包含四個暫存器和三個I/O控制埠，四個暫存器分別為一個BYTE的輸入緩衝暫存器、一個BYTE的輸出緩衝器、一個狀態暫存器及一個控制暫存器。 三個I/O控制埠的定義如下表： PORT #1 Port 1 [ Input Port ] Pin Name Function 0 P10 Keyboard Data [PS/2] 1 P11 Mouse Data [PS/2] 2 P12 3 P13 4 P14 External ROM 1:Enable  0:Disable 5 P15 Manufacturing Setting 1:Enable 0:Disable 6 P16 Display Type Switch 1:Color 0:Monochrome 7 P17 Keyboard Inhibit Switch 1:Enable 0:Disable PORT #2 Port 2 [ Output Port ] Pin Name Function 0 P20 System Reset 1:Nornal 0:Reset  1 P21 Gate A20 2 P22 Mouse Data [PS/2] 1:Pull Data low 0:High –Z 3 P23 Mouse Clock [PS/2] 1:Pull Data low 0:High –Z 4 P24 Input Buffer Full / Keyboard IBF interrupt [PS/2] 1:Assert IRQ 1 0:De-assert IRQ1 5 P25 Output Buffer Empty / Mouse IBF interrupt [PS/2] 1:Assert IRQ 12 0:De-assert IRQ12 6 P26 Keyboard Clock 1:Pull Clock low 0:High Z 7 P2...
閱讀完整內容

EC 所需知識 - LPC

-
圖片
EC 所需知識 軟體工程師的第一步，先把相關的規範(Specification)了解清楚，就像開發一套軟體之前要先了解需求，才能做出一套符合需求的體。相同的EC工程師就是需要把 LPC / SMBUS / PS2 / Smart Battery 的相關知識，清楚明瞭再進下一步。 LPC Specification 本章節介紹以LPC Interface為主，讓讀者可以從中瞭解LPC Interface 的動作原理及腳位作用。當LPC Interface發生問題時，才能籍著對LPC Interface的瞭解來可以找到問題的解決方法。 LPC的特性 相容於舊系統的 X-BUS 介面 可以定址到 4GB，並且BIOS不受1MB的限制，記憶裝置也不受16MB的限制。 在作業系統上不需要特別安裝驅動程式即可正確運作。 在I/O或MEMORY指令會花費較長的時間，可以要考LPC加入等待狀態 LPC支援的裝置 SUPER I/O – 軟碟控制介面、IR、KBC Audio – AC97 記憶裝置 – BIOS Flash 系統管理控制器 [System Manager Controller ] LPC的方塊圖 系統的指令由CPU傳給HOST-Bridge [ 北橋晶片 ] 經 PCI Bus 傳給 PCI-Bridge [ 南橋晶片 ] 也是上圖的HOST，HOST再將PCI的指令指轉為LPC的指令傳到LPC的裝置，完成指令的傳遞。 LPC的硬體腳位 Signal Direction Description Peripheral Host LAD[3:0] I/O I/O 多功能腳位。可為指令、位址及資料 LFRAME# I O 表示LPC指令的開始傳遞及結束 LRESET# I I PCI介面的RESET信號 LCLK I I LPC介面的信號來源 [ 33MHz ] LDRQ# O I 支援DMA及要取得PCI Bus的控制權才會使用 SERIRQ I/O I/O LPC裝置的中斷信號，假如使用IRQ12的裝置要發出中斷信號在第12的CLCOK時，拉LOW即為IRQ12 CLKRUN# OD I/O...
閱讀完整內容