FPGA sample - Lattice I2C IP (EFB) #2

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 Lattice Diamond Setting

  • Click "IPexpress button" and select "EFB" IPX
  • Select "Project Path" (source code files), "File Name" and "Module Output" is Verilog
  • Click "Customize"

  • Select Primary I2C
    • EFB have 2 I2C controller, suggestion use primary I2C
  • "EFB Enable" tab → "EFB Function Enable" Field → Click "Primary User"

  

  • Configuration Primary I2C
    • Speed is 400KHz
    • Slave Address is "0001001"
  • "I2C" tab → "Primary I2C " Field → "I2C Bus Preformance" is 400KHz → "Slave Address" is 7'b0001001
  • Click "Generate" to generate hardware I2C code
  • Founad hardware I2C IPX in your project files

 範例程式碼

  •  宣告 EFB-IP

 /***********************************************************************
 *                                                                      *
 * EFB Module Instanitiation                                            *
 *                                                                      *
 ***********************************************************************/	   
wire rst_p = ~RST_N ;
efbi2c UUT  ( .wb_clk_i (CLK      ),
              .wb_rst_i (rst_p    ),
              .wb_cyc_i (wb_cyc_i ),
              .wb_stb_i (wb_stb_i ),
              .wb_we_i  (wb_we_i  ),
              .wb_adr_i (wb_adr_i ),
              .wb_dat_i (wb_dat_i ),
              .wb_dat_o (wb_dat_o ), 
              .wb_ack_o (wb_ack_o ),      
              .i2c1_scl (SCL      ),
              .i2c1_sda (SDA      ),
              .i2c1_irqo(i2c1_irq_o) );
  • EFB-IP 的 address / data / control pin 訊號順序
 /////////////////////////////////////////////
//                                          //
//    State Machines Sequential Block       //
//                                          //
//////////////////////////////////////////////   
always @ (posedge CLK or negedge RST_N)
begin 
	if(!RST_N)
	begin 
		wb_dat_i 	<= 8'h00;
		wb_stb_i 	<= 1'b0 ;
		wb_adr_i 	<= 8'h00;
		wb_we_i  	<= 1'b0;   
	end   
	else 
	begin 
		wb_dat_i 	<=  n_wb_dat_i;
		wb_stb_i 	<=  n_wb_stb_i;
		wb_adr_i 	<=  n_wb_adr_i;
		wb_we_i  	<=  n_wb_we_i ;
	end 
end 

always @ (posedge CLK or negedge RST_N)
begin 
	if(!RST_N) 
	begin 
		c_state  	<= 10'h000;
		efb_flag 	<= 1'b0 ;
		dat_count	<= 8'd0;
	end  
	else 
	begin  
		c_state  	<= n_state   ;
		efb_flag 	<= n_efb_flag;
		dat_count 	<= n_dat_count ;
	end  
end
  • EFB-IP state machine 加入 oem 程序碼
//////////////////////////////////////////////
//                                          //
//    State Machines Combinational Block    //
//                                          //
//////////////////////////////////////////////   
always @ ( * )
begin 
		n_efb_flag    	= 1'b0 ; 
		n_state       	= c_state ; 
		n_dat_count   	= dat_count ;
		n_wb_dat_i    	= 8'h00;
		n_wb_stb_i    	= 1'b0 ;
		n_wb_adr_i    	= 8'h00;
		n_wb_we_i     	= 1'b0;
		n_temp0       	= temp0;
		i2c_cmd_d     	= i2c_cmd_q;
		i2c_check_d   	= i2c_check_q;
		i2c_data_d    	= i2c_data_q;  
		cmdVRMEn_d	  	= cmdVRMEn_q;	
  
    case(c_state)
    `state0 : // I2C in idle 
    begin 
		n_wb_dat_i 		= 8'h00;
        n_wb_stb_i 		= 1'b0;
        n_wb_adr_i 		= 8'h00;
        n_wb_we_i  		= 1'b0;           
        n_wb_stb_i 		= 1'b0;    
        n_state 		= `state1 ;              
    end   
    
	`state1 : // Enable I2C Interface 
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			n_state 	= `state2;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_adr_i 	= `MICO_EFB_I2C_CR;
			n_wb_dat_i 	= 8'h88;
			n_wb_we_i 	= `WRITE;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end

	`state2 : // Clock Disable 
	begin 		
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			n_state 	= `state3;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_adr_i 	= `MICO_EFB_I2C_CMDR;
			n_wb_dat_i 	= 8'h04;
			n_wb_we_i 	= `WRITE;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
  
	`state3 : // Wait for not BUSY  
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			if(wb_dat_o & ( `MICO_EFB_I2C_SR_BUSY) )
				n_state = c_state;
			else
				n_state = `state4;
		end
		else if(!wb_ack_o) 
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
  
	`state4 : // Discard data 1 
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			n_temp0 	= wb_dat_o; 
			n_state 	= `state5;
		end
		else if(!wb_ack_o) 
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_DATA;
			n_wb_adr_i 	= `MICO_EFB_I2C_RXDR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
 
 
	`state5 : // Discard data 2 
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i = `ALL_ZERO ;
			n_wb_adr_i = `ALL_ZERO ;
			n_wb_we_i =  `LOW ;
			n_wb_stb_i = `LOW ;
			n_efb_flag = `LOW ;
			n_temp0 = wb_dat_o; 
			n_state = `state7;   // keep clock stretching disabled per PCN#10A-13
		end
		else if(!wb_ack_o) 
		begin
			n_efb_flag = `HIGH ;
			n_wb_we_i =  `READ_DATA;
			n_wb_adr_i = `MICO_EFB_I2C_RXDR;
			n_wb_dat_i =  0 ;
			n_wb_stb_i = `HIGH ; 
			n_state = c_state; 
		end
	end
 
	`state7: // wait for data to come
	begin 	
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i = `ALL_ZERO ;
			n_wb_adr_i = `ALL_ZERO ;
			n_wb_we_i =  `LOW ;
			n_wb_stb_i = `LOW ;
			n_efb_flag = `LOW ;
			if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)) 
				n_state = `state8;		   
			else
				n_state = c_state;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag = `HIGH ;
			n_wb_we_i =  `READ_STATUS;
			n_wb_adr_i = `MICO_EFB_I2C_SR;
			n_wb_dat_i =  0 ;
			n_wb_stb_i = `HIGH ; 
			n_state = c_state; 
		end
	end

	`state8: // Store i2C Command Information 
	begin 
		if (wb_ack_o && efb_flag) begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	=  `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			i2c_cmd_d 	= wb_dat_o; 
			n_state 	= `state9;
       end
       else if(!wb_ack_o)
	   begin
			n_efb_flag = `HIGH ;
			n_wb_we_i =  `READ_DATA;
			n_wb_adr_i = `MICO_EFB_I2C_RXDR;
			n_wb_dat_i =  0 ;
			n_wb_stb_i = `HIGH ; 
			n_state = c_state; 
		end
	end
  
	`state9 : // Send ACK or NACK Based upon Command Receive & Wait for Stop `state 17 
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			
			// oem command
		end      
		else 
		begin if(!wb_ack_o)
			n_efb_flag 	= `HIGH ;
			n_wb_adr_i 	= `MICO_EFB_I2C_CMDR;
			n_wb_dat_i 	= {4'h0,~cmd_data,3'b100};    
			n_wb_we_i 	= `WRITE;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
 
 
	`state10 : // Command Valid 
	begin         
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			if(wb_dat_o & ( `MICO_EFB_I2C_SR_TRRDY) )
				n_state = `state11;
			else if (~wb_dat_o[6])		// if stop bit
				n_state = `state2;
			else
				n_state = c_state;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
 
 
	`state11: // Store checksum byte Information
	begin 	
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			i2c_check_d = wb_dat_o;
			if(command_data == ~i2c_check_d) 
			begin			
				// oem command
			end 
			else
				n_state = `state17;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_DATA;
			n_wb_adr_i 	= `MICO_EFB_I2C_RXDR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
 
 
	`state12: // Wait for TRRDY Bit 
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			if(wb_dat_o & ( `MICO_EFB_I2C_SR_TRRDY))
			begin
				// Read command
			end 
			else if (~wb_dat_o[6])
				n_state = `state2;		
			else
				n_state = c_state;
		end    
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
    end
 
	`state13: // Check for read or write operation Go to State15
	begin 	
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			if(wb_dat_o & ( `MICO_EFB_I2C_SR_SRW))
				n_state = `state15;
			else
				n_state = c_state;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
 
 
	`state14: 
	begin // Read Data
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			n_dat_count = dat_count - 1;
			i2c_wr_data[n_dat_count] <= wb_dat_o;		  
			n_state 	= `state19;			 
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_DATA;
			n_wb_adr_i 	= `MICO_EFB_I2C_RXDR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
     end
	 
	`state15: // Send Data to Master
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			n_state 	= `state18;
		    n_dat_count = dat_count - 1 ;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_adr_i 	= `MICO_EFB_I2C_TXDR;
			if(n_dat_count != 1)
				n_wb_dat_i = i2c_cmd_q;
			else
				n_wb_dat_i = i2c_data_q;
			n_wb_we_i 	= `WRITE;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
  end
 
 
 
	`state16: // Send NACK Based upon Command Receive
	begin 	
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
        //  n_count_en 	= `LOW ;
			n_state 	= `state17;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_adr_i 	= `MICO_EFB_I2C_CMDR;
			n_wb_dat_i 	= 8'h0C; 
			n_wb_we_i 	= `WRITE;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
     end
 
 
	`state17: // Wait till Stop is Send 
	begin 
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			if(~wb_dat_o[6])
				n_state = `state2;
			else
				n_state = c_state;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
 
	`state18: // Wait for TxRDY flag and send data again if required 
	begin 	
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
			if ( dat_count == 8'h00) 	   
				n_state = `state16;	// Send Nack for Any More Read Request 
			else if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY ))
     		    n_state = `state15;                   // Send Data  
			else
				n_state = c_state;
		end
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
     end

 
   `state19: // Wait for TRRDY bit 
	begin  
		if (wb_ack_o && efb_flag) 
		begin
			n_wb_dat_i 	= `ALL_ZERO ;
			n_wb_adr_i 	= `ALL_ZERO ;
			n_wb_we_i 	= `LOW ;
			n_wb_stb_i 	= `LOW ;
			n_efb_flag 	= `LOW ;
	        if ( dat_count == 8'h00)
				n_state = `state16;		   
			else if(wb_dat_o & ( `MICO_EFB_I2C_SR_TRRDY) )
				n_state = `state14;
			else if (~wb_dat_o[6])
				n_state = `state2;
			else
				n_state = c_state;
		end 
		else if(!wb_ack_o)
		begin
			n_efb_flag 	= `HIGH ;
			n_wb_we_i 	= `READ_STATUS;
			n_wb_adr_i 	= `MICO_EFB_I2C_SR;
			n_wb_dat_i 	= 0 ;
			n_wb_stb_i 	= `HIGH ; 
			n_state 	= c_state; 
		end
	end
	endcase
end

 

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EC 所需知識 軟體工程師的第一步，先把相關的規範(Specification)了解清楚，就像開發一套軟體之前要先了解需求，才能做出一套符合需求的體。相同的EC工程師就是需要把 LPC / SMBUS / PS2 / Smart Battery 的相關知識，清楚明瞭再進下一步。 SMBUS SMBus [System Management Bus] 是由Intel所制訂的，主要由兩條線組成，其一為CLOCK線，另一條為DATA線。其作用是讓系統監控者透過SMBus來蒐集系統上裝置的資訊如電池的容量、CPU的溫度等，讓系統監控者可以依照所得的資訊通知作業系統做電源管理的處理。在筆記型電腦系統中的ACPI-EC為SMBus的主控者 [Host] 來蒐集SMBus上的裝置資訊回報給作業系統，讓作業系統依使用者的設定做系統電源的管理。 SMBus相關的規格包含SMBus、Smart Selector、Smart Charger及Smart Battery都是ACPI-EC工程師需要瞭解的規格，以下的章節將會詳盡的介紹各個規格的資訊。 SMBUS Specification Hardware Define SMBUS 的硬體線路 –SMBUS由二條線所組成，所有的SMBUS的裝置都並聯在SMBUS上，因此，SMBUS上的所有裝置都需要使用Open collection 或者 Open drain才允許跨接在SMBUS上面，因此線路上必須加上提升電阻來確認SMBUS上的訊號可以正確無誤的傳遞。 如同上圖，有時侯  SMBUS  上會有不同 VDD 的裝置，所以一般在輸入接腳會加稽納二極體保護裝置。不過大部分的作法，會使用電壓緩衝IC來處理不同電壓的 I2C 裝置。  SMBUS電氣上的要求 名稱 說明 值域 單位 下限 上限 VIL 輸入低電位 0.8 V VIH 輸入高電位 2.1 VDD V VOL 輸出為低電位 0.4 V IPULLUP 提升電流值 100 350 uA VDD 工作電壓 2.7 5.5 V SMBUS的時脈要求 名稱 說明 值域 單位
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EC 所需知識 - KBC

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EC 所需知識 軟體工程師的第一步，先把相關的規範(Specification)了解清楚，就像開發一套軟體之前要先了解需求，才能做出一套符合需求的體。相同的EC工程師就是需要把 LPC / SMBUS / PS2 / KBC 等相關知識，清楚明瞭再進下一步。 Keyboard Controller 最早的鍵盤控制器是Intel 8042，主要包含四個暫存器和三個I/O控制埠，四個暫存器分別為一個BYTE的輸入緩衝暫存器、一個BYTE的輸出緩衝器、一個狀態暫存器及一個控制暫存器。 三個I/O控制埠的定義如下表： PORT #1 Port 1 [ Input Port ] Pin Name Function 0 P10 Keyboard Data [PS/2] 1 P11 Mouse Data [PS/2] 2 P12 3 P13 4 P14 External ROM 1:Enable  0:Disable 5 P15 Manufacturing Setting 1:Enable 0:Disable 6 P16 Display Type Switch 1:Color 0:Monochrome 7 P17 Keyboard Inhibit Switch 1:Enable 0:Disable PORT #2 Port 2 [ Output Port ] Pin Name Function 0 P20 System Reset 1:Nornal 0:Reset  1 P21 Gate A20 2 P22 Mouse Data [PS/2] 1:Pull Data low 0:High –Z 3 P23 Mouse Clock [PS/2] 1:Pull Data low 0:High –Z 4 P24 Input Buffer Full / Keyboard IBF interrupt [PS/2] 1:Assert IRQ 1 0:De-assert IRQ1 5 P25 Output Buffer Empty / Mouse IBF interrupt [PS/2] 1:Assert IRQ 12 0:De-assert IRQ12 6 P26 Keyboard Clock 1:Pull Clock low 0:High Z 7 P27 Keyboar
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EC 所需知識 - LPC

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EC 所需知識 軟體工程師的第一步，先把相關的規範(Specification)了解清楚，就像開發一套軟體之前要先了解需求，才能做出一套符合需求的體。相同的EC工程師就是需要把 LPC / SMBUS / PS2 / Smart Battery 的相關知識，清楚明瞭再進下一步。 LPC Specification 本章節介紹以LPC Interface為主，讓讀者可以從中瞭解LPC Interface 的動作原理及腳位作用。當LPC Interface發生問題時，才能籍著對LPC Interface的瞭解來可以找到問題的解決方法。 LPC的特性 相容於舊系統的 X-BUS 介面 可以定址到 4GB，並且BIOS不受1MB的限制，記憶裝置也不受16MB的限制。 在作業系統上不需要特別安裝驅動程式即可正確運作。 在I/O或MEMORY指令會花費較長的時間，可以要考LPC加入等待狀態 LPC支援的裝置 SUPER I/O – 軟碟控制介面、IR、KBC Audio – AC97 記憶裝置 – BIOS Flash 系統管理控制器 [System Manager Controller ] LPC的方塊圖 系統的指令由CPU傳給HOST-Bridge [ 北橋晶片 ] 經 PCI Bus 傳給 PCI-Bridge [ 南橋晶片 ] 也是上圖的HOST，HOST再將PCI的指令指轉為LPC的指令傳到LPC的裝置，完成指令的傳遞。 LPC的硬體腳位 Signal Direction Description Peripheral Host LAD[3:0] I/O I/O 多功能腳位。可為指令、位址及資料 LFRAME# I O 表示LPC指令的開始傳遞及結束 LRESET# I I PCI介面的RESET信號 LCLK I I LPC介面的信號來源 [ 33MHz ] LDRQ# O I 支援DMA及要取得PCI Bus的控制權才會使用 SERIRQ I/O I/O LPC裝置的中斷信號，假如使用IRQ12的裝置要發出中斷信號在第12的CLCOK時，拉LOW即為IRQ12 CLKRUN# OD I/O
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