FPGA sample - Lattice I2C IP (EFB) #1
Lattice I2C IP
Block Diagram
EFB-IP Register
wb_adr | Description | |
MICO_EFB_I2C_CR | 0x40 0x4A | Control Register b[7] : I2C controller enable b[6] : I2C GC mode enable (I2C 廣播模式) b[5] : I2C controller wake-up enable |
MICO_EFB_I2C_CMDR | 0x41 0x4B | Command Register b[7] : STA - Generate (Repeated) START condition b[6] : STO - Generate STOP condition b[5] : RD - I2C read from slave b[4] : WR - I2C write to slave b[3] : ACK - I2C Acknowledge. 0=Send ACK / 1=Send NACK b[2] : CKSDIS - Clock Stretching disable. 0=Enabled / 1=Disabled |
MICO_EFB_I2C_BLOR | 0x42 0x4C | Clock Pre-scale Register |
MICO_EFB_I2C_BHIR | 0x43 0x4D | Clock Pre-scale Register |
MICO_EFB_I2C_TXDR | 0x44 0x4E | Transmit Data Register |
MICO_EFB_I2C_SR | 0x45 0x4F | Status Register b[7] : TIP - Transmitting In Progress. 1=completed / 0=in progress b[6] : BUSY - Bus busy b[5] : RARC - Received Acknowledge. 1=No Ack / 0=Ack b[4] : SRW - Slave RW. 1=Master recv and Slave tran / 0= Master tran and Slave recv b[3] : ARBL - Arbitration Lost. 1=Lost / 0=Normal b[2] : TRRDY - Transmitter or Receiver Ready. 1=ready / 0=not ready b[1] : TROE - Transmitter or Receiver Overrun. 1=Overrun / 0=Normal b[0] : HGC - Hardware General Call Received. 1=Hardware GC / 0=No Hardware GC |
MICO_EFB_I2C_GCDR | 0x46 0x50 | General Call Register |
MICO_EFB_I2C_RXDR | 0x47 0x51 | Receive Data Register |
MICO_EFB_I2C_IRQSR | 0x48 0x52 | IRQ |
MICO_EFB_I2C_IRQENR | 0x49 0x53 | IRQ Enable |
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