Atmel Tiny 88 - TWI module (I2C Slave)
Two-wire Serial Interface (TWI)
TWI 由 clock (SCK) 和 data (SDA) 雙向的接腳所組成,TWI 接腳的設計為開路集閘需要外加 Pull-up 電阻才能資料傳遞。 TWI 的特性如下:
- 最多能支援 128 不同位址的裝置
- 相容於 Philips I2C protocol
- 支援 Standard model (< 100K bps) 和 Fast mode (< 400K bps)
- 支援 Address 喚醒裝置由 Sleep mode
TWI address 和 data packet format
TWI 資料傳輸由 Master 初始化,資料封包由 Start bit 開始,到 Stop bit 結束。
- Start / repeat Start condition : A high to low transition on the SDA line while SCL is high.
- Stop condition : A low to high transition on the SDA line while SCL is high.
- Data packet :
- Read data bit : read SDA bit value when a low to high transition on the SCL
- Write data bit : write SDA bit value when a high to low transition on the SCL
- Address packet : 7-bit address bit + R/W bit + ack/nack
- Data packet : 8-bit data + ack/nack
Register
- TWI Status Register (TWSR)
- TWS (TWI Status)
- Formats and States in the Slave Receiver Mode
- 在接受到 Master 的 start-bit , Slave address, w-bit 之後,若接收的資料是正確的話,TWS=0x60,再依 Slave address 相符回覆 Master Acknowledge 或 not Acknowledge ;若資料不正確的話,TWS=0x68,並回覆 not Acknowledge。
- 在接收到 Master 的資料,TWS = 0x80,再回覆 Master Acknowledge。
- 在接收到 Master 的最後一筆資料,TWS = 0x88,再回覆 Master not Acknowledge。
- 在接收到 Master 的 stop-bit,TWS = 0xA0
- 對於沒有設定 Slave address 的 general call 之後,當接收的資料是正確的話,TWS=0x70;若資料不正確的話,TWS=0x78。
- 在接收到 Master 的資料,TWS = 0x90,再回覆 Master Acknowledge。
- 在接收到 Master 的最後一筆資料,TWS = 0x98,再回覆 Master not Acknowledge。
- 在接收到 Master 的 stop-bit,TWS = 0xA0
- Formats and States in the Slave Transmitter Mode
- 在接受到 Master 的 repeat-start-bit , Slave address, r-bit 之後,若接收的資料是正確的話,TWS=0xA8,再依 Slave address 相符回覆 Master Acknowledge 或 not Acknowledge ;若資料不正確的話,TWS=0xB0,並回覆 not Acknowledge。
- 在傳送給 Master 的資料後,Master 回覆 Acknowledge, TWS = 0xB8。
- 在傳送給 Master 的最後一筆資料後,Master 回覆 not Acknowledge, TWS = 0xC0。
- 在傳送給 Master 的最後一筆資料後,Master 回覆 Acknowledge,TWS = 0xC8。
- TWPS (TWI Prescaler Bits) - bit rate prescaler
- TWI Control Register (TWCR)
- TWINT Flag = 1
- TWI has transmitted a START/REPEATED START condition
- TWI has transmitted SLA+R/W
- TWI has transmitted an address byte
- TWI has lost arbitration
- TWI has been addressed by own Slave address or general call
- TWI has received a data byte
- a STOP or REPEATED START has been received while still addressed as a Slave
- a bus error has occurred due to an illegal START or STOP condition
- TWI Address Register (TWAR)
範例
Microchip AVR311 sample code
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