FPGA sample - 如何使用七段顯示器

在範例中,會使用一個 12 位元計數器,每一秒會加一,再把計數器的值使用七段顯示器,把它顯示出來.

整個範例的方塊圖如下:

範例方塊可以分成:

• 1 second timer : 使用一個 50_000_000 的計數器, 因為輸入時脈為 50MHz, 計數到 50_000_000 就剛好 1 second.
• 12 bits counter : 每一秒將計數器加一.
• 7 segment led : 把 12 bits counter 的值, 轉成七段顯示器的控制碼.
• 7 bits counter : 用來選擇那一個七段顯示器顯示 12 bits counter 的值. 使用視覺暫留的原理,讓數值看起來是一起顯示的.

1 second timer 的程式碼 :

reg[31:0] T1secTimer;		// value of 1 second timer																

//-----------------------------------------------------------
// function 			: 1 sec timer
// input 			: clk (clock) 50MHz
//				: rst_n (reset) 
// output			: none
//-----------------------------------------------------------
always @ (posedge clk or negedge rst_n)										
	if(!rst_n)					  									
		T1secTimer <= 31'd0;	// reset state
	else if(T1secTimer >= 31'd50_000_000) 	
		T1secTimer <= 31'd0;	// 1 second timer timeout 
	else 											
		T1secTimer <= T1secTimer+1'b1;						
	
wire timer_1s = (T1secTimer == 31'd50_000_000);	

12 bits counter 的程式碼 :

reg[11:0] counter;															

//-----------------------------------------------------------
// function 			: counter by 1 second
// input 			: clk (clock) 50MHz
//				: rst_n (reset) 
// output			: none
//-----------------------------------------------------------
always @ (posedge clk or negedge rst_n)										
	if(!rst_n)					 				
		counter <= 12'd0;		// reset state
	else if(timer_1s) 	
		counter <= counter+1'b1;
	else ;		

7 segment led decoder 的程式碼 :

reg[3:0] SegLedData;																													
	
//-----------------------------------------------------------
// function 			: display byte of counter
// input 			: clk (clock) 50MHz
//				: rst_n (reset) 
// output			: none
//-----------------------------------------------------------
always @ (posedge clk or negedge rst_n) 									
	if(!rst_n) 		
		SegLedData <= 4'd0;
	else begin
		case(T1secTimer[8:7])
			2'b00:	// display nibble #0 of counter 
			begin													
				seg_cs <= 3'b100;
				SegLedData <= counter[3:0];
			end

			2'b01: 	// display nibble #1 of counter
			begin												
				seg_cs <= 3'b010; 
				SegLedData <= counter[7:4];
			end

			2'b10: 	// display nibble #2 of counter
			begin												
				seg_cs <= 3'b001; 
				SegLedData <= counter[11:8];
			end

			default: ;
		endcase
	end				

//-------------------------------------------------
// bit assign : DP.G.F.E.D.C.B.A
// 0 : On / 1 : Off
//-------------------------------------------------
parameter 	SEG_NUM0 	= 8'hC0,	//c0,										
		SEG_NUM1 	= 8'hF9,	//f9,
		SEG_NUM2 	= 8'hA4,	//a4,
		SEG_NUM3 	= 8'hB0,	//b0,
		SEG_NUM4 	= 8'h99,	//99,
		SEG_NUM5 	= 8'h92,	//92,
		SEG_NUM6 	= 8'h82,	//82,
		SEG_NUM7 	= 8'hF8,	//F8,
		SEG_NUM8 	= 8'h80,	//80,
		SEG_NUM9 	= 8'h90,	//90,
		SEG_NUMA 	= 8'h88,	//88,
		SEG_NUMB 	= 8'h83,	//83,
		SEG_NUMC 	= 8'hC6,	//c6,
		SEG_NUMD 	= 8'hA1,	//a1,
		SEG_NUME 	= 8'h86,	//86,
		SEG_NUMF 	= 8'h8E;	//8e;	

//-----------------------------------------------------------
// function 			: display nibble of counter
// input 			: 
// output			: none
//-----------------------------------------------------------
always @(SegLedData) begin												
	case(SegLedData) 
		4'h0: seg_data <= SEG_NUM0;
		4'h1: seg_data <= SEG_NUM1;
		4'h2: seg_data <= SEG_NUM2;
		4'h3: seg_data <= SEG_NUM3;
		4'h4: seg_data <= SEG_NUM4;
		4'h5: seg_data <= SEG_NUM5;
		4'h6: seg_data <= SEG_NUM6;
		4'h7: seg_data <= SEG_NUM7;
		4'h8: seg_data <= SEG_NUM8;
		4'h9: seg_data <= SEG_NUM9;
		4'ha: seg_data <= SEG_NUMA;
		4'hb: seg_data <= SEG_NUMB;
		4'hc: seg_data <= SEG_NUMC;
		4'hd: seg_data <= SEG_NUMD;
		4'he: seg_data <= SEG_NUME;
		4'hf: seg_data <= SEG_NUMF;
		default: ;
	endcase			
end			

模組的輸入/輸出接腳

依據使用的開發板,設計模組的輸入/輸出接腳.

範例程式位於 Github 的 FPGA-led-sample